1. Field of the Invention
The present invention relates to computer processor hardware, and, in particular, to field-programmable gate arrays.
2. Description of the Related Art
A field-programmable gate array (FPGA) is an integrated circuit that enables the user to program the functionality to be implemented by the FPGA.
FIG. 1 shows a schematic diagram of a typical FPGA 100. FPGA 100 comprises an array 102 of programmable logic cells (i.e., the logic array), surrounded by a "ring" 104 of programmable input/output (I/O) cells, surrounded by a ring 106 of output nodes (also referred to as "pads"). The I/O cells provide the signal processing interface between the outside world (i.e., exterior to FPGA 100) and the array of logic cells, where the programmed functionality of the FPGA is implemented. The pads are locations where individual physical connections (e.g., wire bonds) are made to transmit data to and from FPGA 100. For each pad, there is a pad circuit within an I/O cell that handles the I/O signal processing for that pad. (For purposes of this specification, pad circuitry refers to "output node circuitry" used to perform I/O signal processing for the output node (i.e., the pad) of an FPGA I/O cell. Those skilled in the art will understand that a logic cell within the FPGA logic array may also have an output node circuit that performs I/O signal processing for an output node of that FPGA logic cell, where that output node connects the logic cell to circuitry external to the logic cell (e.g., I/O cells, other logic cells).)
FIG. 2 shows a simplified block diagram of a typical pad circuit 200 for an I/O cell of FPGA 100 of FIG. 1. Pad circuit 200 comprises an output buffer 202 and an input buffer 204 and handles I/O signal processing between the logic array of FPGA 100 and that portion of the outside world connected to one of the pads of FPGA 100. Output buffer 202 receives output data from the logic array of FPGA 100 for transmission to the pad, and input buffer 204 receives input data presented at the pad from the outside world for transmission to the logic array.
The tri-state signal, presented at a tri-state port of output buffer 202, is a control signal that configures pad circuit 200 for either data input or data output processing. When the tri-state signal is low (i.e., logic 0), pad circuit 200 is configured for data output processing, where the value of the output data signal received at the data-in port of output buffer 202 is presented at the pad. When the tri-state signal is high (i.e., logic 1), pad circuit 200 is configured for data input processing, where the value of the signal presented at the pad is transmitted by input buffer 204 to the logic array as the input data signal. When pad circuit 200 is configured for data input processing, output buffer 202 is essentially turned off and the pad is placed at a relatively high impedance (i.e., tri-state mode). This allows the input data signals presented at the pad, from external sources, to be transmitted by input buffer 204 to the logic array.
When multiple pads, either from the same chip or different chips, are tied to the same wire, it may be desirable to implement a "wired AND" functionality, whereby, if any pad drives a low signal (logic 0), the wire is pulled low (logic 0). This can be achieved by using a pullup on the wire and configuring each pad circuit in open-drain mode, such that, when the data signal is high (logic 1), the corresponding output is in high-impedance data-input mode, letting the wire be pulled up by the pullup, and, when the data signal is low (logic 0), the corresponding output is low.
As described earlier, a tri-state signal of logic 1 will cause the pad circuit to be configured in the high-impedance data-input mode. One way to configure the pad circuit in the open-drain drive mode is to apply the output data signal to the tri-state port of the output buffer. For conventional FPGAs, general routing resources of the FPGA (e.g., programmable routers external to the I/O cells that connect the I/O cells to the logic array) can be used to tie the output data signal to the output buffer's tri-state port, but not without costly consequences.
First of all, using FPGA general routing resources leads to unpredictable and slower performance, in that there could be differences between (1) the time that the output data signal arrives at the data-in port of the output buffer and (2) the time that that same output data signal arrives at the tri-state port of the output buffer. Such differences can lead to delays in the switching of the pad circuit into or out of the high-impedance state that can unacceptably slow down the operations of the system of which the FPGA is a part. Moreover, the general routing resources of an FPGA are finite, and having to use some of those finite resources for the overhead of achieving open-drain drive mode can be inefficient, especially where those resources might otherwise be used to increase the overall programming flexibility of the FPGA.
It is a goal of the present invention to address these limitations of the prior art. Further aspects and advantages of this invention will become apparent from the detailed description which follows.